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    SubjectRe: [BUG] "sched: Remove rq->lock from the first half of ttwu()" locks up on ARM
    On 26 May 2011 13:50, Ingo Molnar <> wrote:
    > * Russell King - ARM Linux <> wrote:
    >> On Thu, May 26, 2011 at 02:26:23PM +0200, Ingo Molnar wrote:
    >> >
    >> > * Peter Zijlstra <> wrote:
    >> >
    >> > > Sort this by reverting to the old behaviour for this situation
    >> > > and perform a full remote wake-up.
    >> >
    >> > Btw., ARM should consider switching most of its subarchitectures
    >> > to !__ARCH_WANT_INTERRUPTS_ON_CTXSW - enabling irqs during
    >> > context switches is silly and now expensive as well.
    >> Not going to happen.  The reason we do it is because most of the
    >> CPUs have to (slowly) flush their caches during switch_mm(), and to
    >> have IRQs off over the cache flush means that we lose IRQs.
    > How much time does that take on contemporary ARM hardware, typically
    > (and worst-case)?

    On newer ARMv6 and ARMv7 hardware, we no longer flush the caches at
    context switch as we got VIPT (or PIPT-like) caches.

    But modern ARM processors use something called ASID to tag the TLB
    entries and we are limited to 256. The switch_mm() code checks for
    whether we ran out of them to restart the counting. This ASID
    roll-over event needs to be broadcast to the other CPUs and issuing
    IPIs with the IRQs disabled isn't always safe. Of course, we could
    briefly re-enable them at the ASID roll-over time but I'm not sure
    what the expectations of the code calling switch_mm() are.

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      Last update: 2011-05-26 16:47    [W:2.968 / U:0.096 seconds]
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