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SubjectRe: [PATCH 1/3] perf_events: update Intel extra regs shared constraints management (v3)
On Mon, May 23, 2011 at 06:12:47PM +0200, Stephane Eranian wrote:
>
> This patch improves the code managing the extra shared registers
> used for offcore_response events on Intel Nehalem/Westmere. The
> idea is to use static allocation instead of dynamic allocation.
> This simplifies greatly the get and put constraint routines for
> those events.
>
> The patch also renames per_core to shared_regs because the same
> data structure gets used whether or not HT is on. When HT is
> off, those events still need to coordination because they use
> a extra MSR that has to be shared within an event group.
>
> The first post of this patch had an older (bogus) version of
> the patch with bogus initialization of reg->idx.

I did a quick read -- not full check -- and it looked good to me.
I like the idea of preallocating the slots.

Acked-by: Andi Kleen <ak@linux.intel.com>

-Andi


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