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SubjectRe: [PATCH 0/3] perf_events: update extra shared registers management (v2)
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On Mon, May 23, 2011 at 5:15 PM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, 2011-05-23 at 14:00 +0200, Stephane Eranian wrote:
>> On Mon, May 23, 2011 at 1:10 PM, Peter Zijlstra <peterz@infradead.org> wrote:
>> > On Mon, 2011-05-23 at 12:58 +0200, Stephane Eranian wrote:
>> >> There is a major issue as it stands, though. You can
>> >> get into an infinite loop bouncing between RSP_0 and RSP_1
>> >> in case there is no solution in the group, i.e., you have 3 values
>> >> for the extra MSR. I think you need to count the number of times
>> >> you've called intel_try_alt_er() with success or maintain some sort
>> >> of bitmask of possible alternate choices and when you exhaust that,
>> >> you simply fail.
>> >
>> > That should be sorted by the compare with the initial idx value, no?
>> > Once its back where it started out it'll bail.
>> >
>> Nope.
>>
>> Take:
>>   - ev1=rsp_0:0x1001
>>   - ev2=rsp_0:0x1002
>>   - ev3=rsp_1:0x1008
>>
>> ev1-> rsp_0
>> ev2-> rsp_0, conflict, then try yields rsp_1 -> ok
>> ev3 -> rsp_1, conflict, then rsp_0, but fails, try again -> rsp_1,
>> fails, and so on
>>
>> The issue is that the intel_try() function does not know the
>> history of the swaps between rsp_0, rsp1.
>
> But it does, we pass the initial reg->idx in, and return false when that
> matches the new idx, so in your example, ev3 will do:
>
>     rsp_1 -> conflict,
>  try rsp_0 -> conflict,
>  try rsp_1 -> bail, return emptyconstraint
>
>
Ok, my fault. That's because I tweaked your patch a bit and
I did not keep track of idx. I guess the logic is not obvious.
I think you should rename idx to orig_idx.


>
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