Messages in this thread | | | Subject | Re: [PATCH 0/3] perf_events: update extra shared registers management (v2) | From | Peter Zijlstra <> | Date | Mon, 23 May 2011 13:10:26 +0200 |
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On Mon, 2011-05-23 at 12:58 +0200, Stephane Eranian wrote: > There is a major issue as it stands, though. You can > get into an infinite loop bouncing between RSP_0 and RSP_1 > in case there is no solution in the group, i.e., you have 3 values > for the extra MSR. I think you need to count the number of times > you've called intel_try_alt_er() with success or maintain some sort > of bitmask of possible alternate choices and when you exhaust that, > you simply fail.
That should be sorted by the compare with the initial idx value, no? Once its back where it started out it'll bail.
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