lkml.org 
[lkml]   [2011]   [May]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH v1 RESEND] audio: tlv320aic26: fix PLL register configuration
From
Date
On Fri, 2011-05-20 at 10:26 -0400, Michael Williamson wrote:
> The current PLL configuration code for the tlc320aic26 codec appears to assume a
> hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS
> API for the calculation.
>
> Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.
>
> Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
> ---
> This got bounced by the alsa-devel list (I wasn't on list). I'm not sure
> whose tree this needs to go through, but given the lack of response
> I'm guessing alsa-devel. If I'm missing a list, any advice would be
> appreciated.

Applied.

Thanks

Liam



\
 
 \ /
  Last update: 2011-05-21 13:11    [W:0.026 / U:0.448 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site