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SubjectRe: [PATCH v1 RESEND] audio: tlv320aic26: fix PLL register configuration
On Fri, 2011-05-20 at 10:26 -0400, Michael Williamson wrote:
> The current PLL configuration code for the tlc320aic26 codec appears to assume a
> hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS
> API for the calculation.
> Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.
> Signed-off-by: Michael Williamson <>
> Acked-by: Mark Brown <>
> ---
> This got bounced by the alsa-devel list (I wasn't on list). I'm not sure
> whose tree this needs to go through, but given the lack of response
> I'm guessing alsa-devel. If I'm missing a list, any advice would be
> appreciated.




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