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SubjectRe: [PATCH] cpu, AMD: Fix another bug in the new errata checking code
On 05/16/2011 08:43 AM, Chuck Ebbert wrote:
> On Fri, 13 May 2011 17:19:23 +0200
> Hans Rosenfeld<hans.rosenfeld@amd.com> wrote:
>>>>> Could you send me the contents of MSRs 0xc0010140, 0xc0010141 and
>>>>> 0xc0010055?
>>>>
>>>> Knowing whether any C state above C1 is declared could be useful too.
>>>>
>>> rdmsr 0xc0010140 gives 2
>>
>> This means that E400 is known ...
>>
>>> rdmsr 0xc0010141 gives 0
>>
>> ... and no workaround is necessary ...
>>
>>> rdmsr 0xc0010055 gives 0
>>
>> ... because C1E is not enabled.
>>
>>> And ARAT is definitely set where it wasn't before these updates.
>>
>> I don't see how that could possibly make a difference if C1E is not even
>> enabled. This is all very strange.
>>
>
> Looking at commit e20a2d205c05cef6b5783df339a7d54adeb50962 ("x86, AMD: Fix
> APIC timer erratum 400 affecting K8 Rev.A-E processors") I see that it
> extended the E400 workaround to cover a whole range of processors that
> have never supported C1E. Isn't this just more of the same problem, only
> happening with processors that support C1E but have it disabled?

Erratum 400 covers not just C1E but also C3 and the latter is not
covered by OSVW so we may need to update cpu_has_amd_erratum().
Fortunately, only a few processors in family 10h support C3. I think, in
fact, it's only the part that you have (model 6 stepping 2) but we need
to confirm it. If you know of other FMSs please let us know.

As for expansion of ranges covering this erratum in that commit, it only
affected family fh.

>
> They are using C3 for idle states, I can confirm that now.

Thanks.

-boris




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