lkml.org 
[lkml]   [2011]   [May]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: Question: GPIO driver how to get irq_base
Date
Hi,

Pch_gpio driver can become detecting falling/rising edge.
I attached the latest GPIO driver, usermode TP and the result.

However, "poll( )" of gpio_tp behavior is different than I anticipated.
The "poll" is not blocked. (The returned value looks good)

My anticipated behavior is
Execute gpio_tp (blocked at poll( ))
(Detect edge)
Interrupt handler of pch_gpio is called
Blocked poll( ) becomes released.

Let me know your opinion.

With Best Regards,
-----------------------------------------
Tomoya MORINAGA
OKI SEMICONDUCTOR CO., LTD.
#include <stdio.h>
#include <unistd.h>
#include <poll.h>
#include <fcntl.h>
#define GPIO_DIR "/sys/class/gpio"
#define GPIO_NAME "gpio246"
#define GPIO_PATH GPIO_DIR "/" GPIO_NAME "/"
int main(void)
{
int fd;
int i;
int ret;
fd = open(GPIO_PATH "direction", O_RDWR);
printf("fd=%d\n", fd);
ret = write(fd, "in", 2);
printf("write=%d\n", ret);
close(fd);
fd = open(GPIO_PATH "edge", O_RDWR);
printf("fd=%d\n", fd);
// ret=write(fd, "rising", 6);
ret=write(fd, "falling", 7);
printf("write=%d\n", ret);
close(fd);
for (i=0; i < 3; i++) {
char val;
struct pollfd pfd;
fd = open(GPIO_PATH "value", O_RDWR);
printf("fd=%d\n", fd);

ret=read(fd, &val, 1);
printf("read=%d val=%c\n", ret, val);
printf("waiting for interrupt..."); fflush(stdout);
pfd.fd = fd;
pfd.events = POLLIN;
pfd.revents = 0;
ret = poll(&pfd, 1, -1);
printf("poll=%d revent=0x%x\n", ret, pfd.revents);
ret=lseek(fd, 0, SEEK_SET);
printf("lseek=%d\n", ret);
ret = read(fd, &val, 1);
printf("read=%d val=%c\n", ret, val);
close(fd);
printf("OK (%c, %s)\n", val, val == '0' ? "Low" : "High");
usleep(100000);
}
return 0;
}
/*
* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
#define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */

#define PCH_EDGE_FALLING 0
#define PCH_EDGE_RISING BIT(0)
#define PCH_LEVEL_L BIT(1)
#define PCH_LEVEL_H (BIT(0) | BIT(1))
#define PCH_EDGE_BOTH BIT(2)
#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))

#define PCH_IRQ_BASE 20

struct pch_regs {
u32 ien;
u32 istatus;
u32 idisp;
u32 iclr;
u32 imask;
u32 imaskclr;
u32 po;
u32 pi;
u32 pm;
u32 im0;
u32 im1;
u32 reserved[4];
u32 reset;
};

/**
* struct pch_gpio_reg_data - The register store data.
* @po_reg: To store contents of PO register.
* @pm_reg: To store contents of PM register.
*/
struct pch_gpio_reg_data {
u32 po_reg;
u32 pm_reg;
};

/**
* struct pch_gpio - GPIO private data structure.
* @base: PCI base address of Memory mapped I/O register.
* @reg: Memory mapped PCH GPIO register list.
* @dev: Pointer to device structure.
* @gpio: Data for GPIO infrastructure.
* @pch_gpio_reg: Memory mapped Register data is saved here
* when suspend.
* @lock: spin_lock variable
*/
struct pch_gpio {
void __iomem *base;
struct pch_regs __iomem *reg;
struct device *dev;
struct gpio_chip gpio;
struct pch_gpio_reg_data pch_gpio_reg;
struct mutex lock;
int irq_base;
spinlock_t spinlock;
};

static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
u32 reg_val;
struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);

mutex_lock(&chip->lock);
reg_val = ioread32(&chip->reg->po);
if (val)
reg_val |= (1 << nr);
else
reg_val &= ~(1 << nr);

iowrite32(reg_val, &chip->reg->po);
mutex_unlock(&chip->lock);
}

static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);

return ioread32(&chip->reg->pi) & (1 << nr);
}

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
int val)
{
struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
u32 pm;
u32 reg_val;

mutex_lock(&chip->lock);
pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
pm |= (1 << nr);
iowrite32(pm, &chip->reg->pm);

reg_val = ioread32(&chip->reg->po);
if (val)
reg_val |= (1 << nr);
else
reg_val &= ~(1 << nr);
iowrite32(reg_val, &chip->reg->po);

mutex_unlock(&chip->lock);

return 0;
}

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
u32 pm;

mutex_lock(&chip->lock);
pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
pm &= ~(1 << nr);
iowrite32(pm, &chip->reg->pm);
mutex_unlock(&chip->lock);

return 0;
}

/*
* Save register configuration and disable interrupts.
*/
static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
}

/*
* This function restores the register configuration of the GPIO device.
*/
static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
/* to store contents of PO register */
iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
/* to store contents of PM register */
iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
}

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
return chip->irq_base + offset;
}

static void pch_gpio_setup(struct pch_gpio *chip)
{
struct gpio_chip *gpio = &chip->gpio;

gpio->label = dev_name(chip->dev);
gpio->owner = THIS_MODULE;
gpio->direction_input = pch_gpio_direction_input;
gpio->get = pch_gpio_get;
gpio->direction_output = pch_gpio_direction_output;
gpio->set = pch_gpio_set;
gpio->dbg_show = NULL;
gpio->base = -1;
gpio->ngpio = GPIO_NUM_PINS;
gpio->can_sleep = 0;
gpio->to_irq = pch_gpio_to_irq;
}

static int pch_irq_type(unsigned irq, unsigned type)
{
u32 im;
u32 *im_reg;
u32 ien;
u32 im_pos;
int ch;
unsigned long flags;
u32 val;
struct pch_gpio *chip = get_irq_chip_data(irq);

ch = irq - chip->irq_base;
if (irq <= chip->irq_base + 7) {
im_reg = &chip->reg->im0;
im_pos = ch;
} else {
im_reg = &chip->reg->im1;
im_pos = ch - 8;
}
dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
__func__, irq, type, ch, im_pos);

spin_lock_irqsave(&chip->spinlock, flags);

if (type == IRQ_TYPE_EDGE_RISING)
val = PCH_EDGE_RISING;
else if (type == IRQ_TYPE_EDGE_FALLING)
val = PCH_EDGE_FALLING;
else if (type == IRQ_TYPE_EDGE_BOTH)
val = PCH_EDGE_BOTH;
else if (type == IRQ_TYPE_LEVEL_HIGH)
val = PCH_LEVEL_L;
else if (type == IRQ_TYPE_LEVEL_LOW)
val = PCH_LEVEL_H;
else if (type == IRQ_TYPE_PROBE)
goto end;
else {
dev_warn(chip->dev, "%s: unknown type(%dd)", __func__, type);
goto end;
}

/* Set interrupt mode */
im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
iowrite32(im | (val << (im_pos * 4)), im_reg);

/* iclr */
iowrite32(BIT(ch), &chip->reg->iclr);

/* IMASKCLR */
iowrite32(BIT(ch), &chip->reg->imaskclr);

/* Enable interrupt */
ien = ioread32(&chip->reg->ien);
iowrite32(ien | BIT(ch), &chip->reg->ien);
end:
spin_unlock_irqrestore(&chip->spinlock, flags);

return 0;
}

static void pch_irq_unmask(unsigned irq)
{
}

static void pch_irq_mask(unsigned irq)
{
}

static struct irq_chip pch_irqchip = {
.name = "PCH-GPIO",
.mask = pch_irq_mask,
.unmask = pch_irq_unmask,
.set_type = pch_irq_type,
};

static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
struct pch_gpio *chip = dev_id;
u32 reg_val = ioread32(&chip->reg->istatus);
int i;
int ret = IRQ_NONE;

for (i = 0; i < GPIO_NUM_PINS; i++) {
if (reg_val & BIT(i)) {
dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
__func__, i, irq, reg_val);
iowrite32(BIT(i), &chip->reg->iclr);
generic_handle_irq(chip->irq_base + i);
ret = IRQ_HANDLED;
}
}
return ret;
}

static int __devinit pch_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
s32 ret;
struct pch_gpio *chip;
int irq_base;
int i;

chip = kzalloc(sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;

chip->dev = &pdev->dev;
ret = pci_enable_device(pdev);
if (ret) {
dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
goto err_pci_enable;
}

ret = pci_request_regions(pdev, KBUILD_MODNAME);
if (ret) {
dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
goto err_request_regions;
}

chip->base = pci_iomap(pdev, 1, 0);
if (chip->base == 0) {
dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
ret = -ENOMEM;
goto err_iomap;
}

chip->reg = chip->base;
pci_set_drvdata(pdev, chip);
mutex_init(&chip->lock);
pch_gpio_setup(chip);
ret = gpiochip_add(&chip->gpio);
if (ret) {
dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
goto err_gpiochip_add;
}

irq_base = irq_alloc_descs(-1, PCH_IRQ_BASE, GPIO_NUM_PINS, GFP_KERNEL);
if (irq_base < 0) {
dev_err(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
goto err_irq_alloc_descs;
}

chip->irq_base = irq_base;

ret = request_irq(pdev->irq, pch_gpio_handler,
IRQF_SHARED, KBUILD_MODNAME, chip);
if (ret != 0) {
dev_err(&pdev->dev,
"%s request_irq failed\n", __func__);
goto err_request_irq;
}

for (i = 0; i < GPIO_NUM_PINS; i++) {
set_irq_chip_and_handler_name(i + irq_base, &pch_irqchip,
handle_simple_irq, "pch");
set_irq_chip_data(i + irq_base, chip);
}

/* Initialize interrupt ien register */
iowrite32(0, &chip->reg->ien);

return 0;

err_request_irq:
irq_free_descs(irq_base, GPIO_NUM_PINS);

err_irq_alloc_descs:
ret = gpiochip_remove(&chip->gpio);
if (ret)
dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);

err_gpiochip_add:
pci_iounmap(pdev, chip->base);

err_iomap:
pci_release_regions(pdev);

err_request_regions:
pci_disable_device(pdev);

err_pci_enable:
kfree(chip);
dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
return ret;
}

static void __devexit pch_gpio_remove(struct pci_dev *pdev)
{
int err;
struct pch_gpio *chip = pci_get_drvdata(pdev);

err = gpiochip_remove(&chip->gpio);
if (err)
dev_err(&pdev->dev, "Failed gpiochip_remove\n");

pci_iounmap(pdev, chip->base);
pci_release_regions(pdev);
pci_disable_device(pdev);
kfree(chip);
}

#ifdef CONFIG_PM
static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
s32 ret;
struct pch_gpio *chip = pci_get_drvdata(pdev);

pch_gpio_save_reg_conf(chip);
pch_gpio_restore_reg_conf(chip);

ret = pci_save_state(pdev);
if (ret) {
dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
return ret;
}
pci_disable_device(pdev);
pci_set_power_state(pdev, PCI_D0);
ret = pci_enable_wake(pdev, PCI_D0, 1);
if (ret)
dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

return 0;
}

static int pch_gpio_resume(struct pci_dev *pdev)
{
s32 ret;
struct pch_gpio *chip = pci_get_drvdata(pdev);

ret = pci_enable_wake(pdev, PCI_D0, 0);

pci_set_power_state(pdev, PCI_D0);
ret = pci_enable_device(pdev);
if (ret) {
dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
return ret;
}
pci_restore_state(pdev);

iowrite32(0x01, &chip->reg->reset);
iowrite32(0x00, &chip->reg->reset);
pch_gpio_restore_reg_conf(chip);

return 0;
}
#else
#define pch_gpio_suspend NULL
#define pch_gpio_resume NULL
#endif

#define PCI_VENDOR_ID_ROHM 0x10DB
static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

static struct pci_driver pch_gpio_driver = {
.name = "pch_gpio",
.id_table = pch_gpio_pcidev_id,
.probe = pch_gpio_probe,
.remove = __devexit_p(pch_gpio_remove),
.suspend = pch_gpio_suspend,
.resume = pch_gpio_resume
};

static int __init pch_gpio_pci_init(void)
{
return pci_register_driver(&pch_gpio_driver);
}
module_init(pch_gpio_pci_init);

static void __exit pch_gpio_pci_exit(void)
{
pci_unregister_driver(&pch_gpio_driver);
}
module_exit(pch_gpio_pci_exit);

MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL");
[root@localhost morinaga]# ./a.out
fd=3
write=2
fd=3
write=7
fd=3
read=1 val=1
waiting for interrupt...poll=1 revent=0x1
lseek=0
read=1 val=1
OK (1, High)
fd=3
read=1 val=1
waiting for interrupt...poll=1 revent=0x1
lseek=0
read=1 val=1
OK (1, High)
fd=3
read=1 val=1
waiting for interrupt...poll=1 revent=0x1
lseek=0
read=1 val=1
OK (1, High)
[root@localhost morinaga]#

\
 
 \ /
  Last update: 2011-05-16 12:41    [W:0.099 / U:13.668 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site