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    Subject[PATCH v3 2/6] x86-64: Remove unnecessary barrier in vread_tsc
    RDTSC is completely unordered on modern Intel and AMD CPUs.  The
    Intel manual says that lfence;rdtsc causes all previous instructions
    to complete before the tsc is read, and the AMD manual says to use
    mfence;rdtsc to do the same thing.

    From a decent amount of testing [1] this is enough to make rdtsc
    be ordered with respect to subsequent loads across a wide variety
    of CPUs.

    On Sandy Bridge (i7-2600), this improves a loop of
    clock_gettime(CLOCK_MONOTONIC) by more than 5 ns/iter.


    Signed-off-by: Andy Lutomirski <>
    arch/x86/kernel/tsc.c | 9 +++++----
    1 files changed, 5 insertions(+), 4 deletions(-)

    diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
    index bc46566..7cabdae 100644
    --- a/arch/x86/kernel/tsc.c
    +++ b/arch/x86/kernel/tsc.c
    @@ -769,13 +769,14 @@ static cycle_t __vsyscall_fn vread_tsc(void)
    cycle_t ret;

    - * Surround the RDTSC by barriers, to make sure it's not
    - * speculated to outside the seqlock critical section and
    - * does not cause time warps:
    + * Empirically, a fence (of type that depends on the CPU)
    + * before rdtsc is enough to ensure that rdtsc is ordered
    + * with respect to loads. The various CPU manuals are unclear
    + * as to whether rdtsc can be reordered with later loads,
    + * but no one has ever seen it happen.
    ret = (cycle_t)vget_cycles();
    - rdtsc_barrier();

    return ret >= VVAR(vsyscall_gtod_data).clock.cycle_last ?
    ret : VVAR(vsyscall_gtod_data).clock.cycle_last;

     \ /
      Last update: 2011-05-10 16:19    [W:0.022 / U:15.400 seconds]
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