Messages in this thread | | | Subject | Re: [RFC] ARM DMA mapping TODO, v1 | From | Catalin Marinas <> | Date | Thu, 28 Apr 2011 09:31:12 +0100 |
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On Wed, 2011-04-27 at 22:45 +0100, Benjamin Herrenschmidt wrote: > On Wed, 2011-04-27 at 10:52 +0100, Catalin Marinas wrote: > > It's not broken since we moved to using Normal non-cacheable memory > > for the coherent DMA buffers (as long as you flush the cacheable alias > > before using the buffer, as we already do). The ARM ARM currently says > > unpredictable for such situations but this is being clarified in > > future updates and the Normal non-cacheable vs cacheable aliases can > > be used (given correct cache maintenance before using the buffer). > > Don't you have a risk where speculative loads or prefetches might bring > back some stuff into the cache via the cachable mapping ? Is that an > issue ? As long as it's non-dirty and the cachable mapping isn't > otherwise used, I suppose it might be a non-issue, tho I've seen in > powerpc land cases of processors that can checkstop if a subsequent non > cachable access "hits" the stuff that was loaded in the cache.
At the CPU cache level, unexpected cache hit is considered a miss, IOW non-cacheable memory accesses ignore the cache lines that may have been speculatively loaded.
-- Catalin
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