Messages in this thread | | | Date | Mon, 25 Apr 2011 10:50:04 -0400 | From | Don Zickus <> | Subject | Re: [PATCH 3/4] perf, nmi: Move LVT un-masking into irq handlers |
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On Mon, Apr 25, 2011 at 06:15:25PM +0400, Cyrill Gorcunov wrote: > > Don't get me wrong please but the whole picture of what is happening can be seen only when > all caller sequence is taken into account and once (for some reason) the sequence > get changed the "detailed" comment would simply mess the comment reader so I think > the former comment is detailed enough and what is more important it's "general" enough > so it doesn't depend on when code is called but points a reader on hw details and it's > up to a reader to check "current" calling sequence because kernel code changes too > damn fast ;)
I think Ingo is looking for is something like
/* * It has been observed that quirks in the P4 perf hw has forced the * following sequence of events to happen in the order below * * - clear the OVF bit (as it will continue to assert the NMI line) * - unmask the apic LVTPC bit to allow NMIs from the PMU again * - optionally re-enable the PMU to count events again * * Un-masking the apic prematurely (before clearing the OVF bit) has led * to the creation of a second NMI event (which led to the unknown NMI * warnings) due to the fact that the PMU will continue to generate an * interrupt until its OVF bit is cleared. */
Something that specifically documents what we saw, why we saw it and what we are doing to avoid it.
Cheers, Don
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