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SubjectRe: [generalized cache events] Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2
On Sat, Apr 23, 2011 at 9:50 AM, Peter Zijlstra <> wrote:
> On Fri, 2011-04-22 at 17:03 -0700, Andi Kleen wrote:
>> > > Yes, and note that with instructions events we even have skid-less PEBS
>> > > profiling so seeing the precise .
>> >                                   - location of instructions is possible.
>> It was better when it was eaten. PEBS does not actually eliminated
>> skid unfortunately. The interrupt still occurs later, so the
>> instruction location is off.
>> PEBS merely gives you more information.
> You're so skilled at not actually saying anything useful. Are you
> perchance referring to the fact that the IP reported in the PEBS data is
> exactly _one_ instruction off? Something that is demonstrated to be
> fixable?
> Or are you defining skid differently and not telling us your definition?

PEBS is guaranteed to return an IP that is just after AN instruction that
caused the event. However, that instruction is NOT the one at the end
of your period. Let's take an example with INST_RETIRED, period=100000.
Then, the IP you get is NOT after the 100,000th retired instruction. It's an
instruction that is N cycles after that one. There is internal skid due to the
way PEBS is implemented.

That is what Andi is referring to. The issue causes bias and thus impacts
the quality of the samples. On SNB, there is a new INST_RETIRED:PREC_DIST
event. PREC_DIST=precise distribution. It tries to correct for the skid
on this event on INST_RETIRED with PEBS (look at Vol3b).
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