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SubjectRe: [PATCH 1/1] perf tools: Add missing user space support for config1/config2
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On Fri, 2011-04-22 at 16:54 -0700, Andi Kleen wrote:
> >
> > #define SNB_PF_LLC_DATA_RD (1 << 7)
> > #define SNB_PF_LLC_RFO (1 << 8)
> > #define SNB_PF_LLC_IFETCH (1 << 9)
> > #define SNB_BUS_LOCKS (1 << 10)
> > #define SNB_STRM_ST (1 << 11)
> > /* hole */
> > #define SNB_OFFCORE_OTHER (1 << 15)
> > #define SNB_COMMON (1 << 16)
> > #define SNB_NO_SUPP (1 << 17)
> > #define SNB_LLC_HITM (1 << 18)
> > #define SNB_LLC_HITE (1 << 19)
> > #define SNB_LLC_HITS (1 << 20)
> > #define SNB_LLC_HITF (1 << 21)
> > /* hole */
> > #define SNB_SNP_NONE (1 << 31)
> > #define SNB_SNP_NOT_NEEDED (1 << 32)
> > #define SNB_SNP_MISS (1 << 33)
> > #define SNB_SNP_NO_FWD (1 << 34)
> > #define SNB_SNP_FWD (1 << 35)
> > #define SNB_HITM (1 << 36)
> > #define SNB_NON_DRAM (1 << 37)
> >
> > #define SNB_DMND_READ (SNB_DMND_DATA_RD)
> > #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_DMND_WB|SNB_STRM_ST)
> > #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_DATA_RFO)
> >
> > Is what I came up with, but I'm stumped on how to construct:
> >
> > #define SNB_L3_HIT
>
> All the LLC hits together.

Bits 18-21 ?

> Or it can be done with the PEBS memory latency event (like Lin-Ming's patch) or
> with mem_load_uops_retired (but then only for loads)
>
> > #define SNB_L3_MISS
>
> Don't set any of the LLC bits

So a 0 for the response type field? That's not valid. You have to set
some bit between 16-37.

>
> >
> > #define SNB_ALL_DRAM
>
> Just don't set NON_DRAM

So bits 17-21|31-36 for the response type field?

That seems wrong as that would include what we previously defined to be
L3_HIT, which never makes it to DRAM.

> > #define SNB_REMOTE_DRAM
>
> The current client SNBs for which those tables are don't have remote
> DRAM.

So what you're telling us is that simply because Intel hasn't shipped a
multi-socket SNB system yet they either:

1) omitted a few bits from that table,
2) have a completely different offcore response msr just for kicks?

Feh!


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