Messages in this thread | | | Date | Sat, 23 Apr 2011 19:19:07 -0700 | From | Andi Kleen <> | Subject | Re: [generalized cache events] Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2 |
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> You're so skilled at not actually saying anything useful. Are you > perchance referring to the fact that the IP reported in the PEBS data is > exactly _one_ instruction off? Something that is demonstrated to be > fixable?
It's one instruction off the instruction that was retired when the PEBS interrupt was ready, but not one instruction off the instruction that caused the event. There's still skid in triggering the interrupt.
The main good thing about PEBS is that you can get some information about the state of the instruction, just not the EIP. For example with the memory latency event you can actually get the address and memory cache state (as Lin Ming's patchkit implements)
-Andi
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