Messages in this thread | | | Date | Thu, 21 Apr 2011 21:46:15 +0200 | From | Kasper Pedersen <> | Subject | Re: x86: tsc: v2 make TSC calibration more immune to interrupts |
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On 04/21/2011 12:39 AM, Josh Triplett wrote: > > Have you considered disabling interrupts while calibrating? That would > ensure that you only have to care about SMIs, not arbitrary interrupts. > > Also, on more recent x86 systems you could look at MSR_SMI_COUNT (MSR > 0x34) to detect if any SMIs have occurred during the sample period. > rdmsr, start sample period, stop sample period, rdmsr, if delta of 0 > then no SMIs occurred. Exists on Nehalem and newer, at least.
I have now tested this, and it is worth doing.
+ local_irq_save(flags); t1 = get_cycles(); if (hpet) tp = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; else tp = acpi_pm_read_early(); t2 = get_cycles(); + local_irq_restore(flags);
On P3, when no SMI occur, the sample is now always perfect. On Core2 there is still very rare variation - up to 8000 clock, maybe bus contention? Thinking it was cache I tried keeping irqs disabled for 5M iterations, and that makes it occur _more_ often.
Atom shows the same as Core2, but even more rarely.
So, even if we have a Nehalem with SMI counter, the 5 samples will still have benefit.
/Kasper Pedersen -- This is my second patch ever, tell me when I do something wrong.
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