Messages in this thread |  | | From | Mike Frysinger <> | Date | Wed, 13 Apr 2011 18:57:13 -0400 | Subject | Re: freezer: should barriers be smp ? |
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On Wed, Apr 13, 2011 at 18:49, Rafael J. Wysocki wrote: > On Thursday, April 14, 2011, Mike Frysinger wrote: >> i guess the trouble for us is that you have one CPU posting writes to >> task->flags (and doing so by grabbing the task's spinlock), but the >> other CPU is simply reading those flags. there are no SMP barriers in >> between the read and write steps, nor is the reading CPU grabbing any >> locks which would be an implicit SMP barrier. since the Blackfin SMP >> port lacks hardware cache coherency, there is no way for us to know >> "we've got to sync the caches before we can do this read". by using >> the patch i posted above, we have that signal and so things work >> correctly., > > In theory I wouldn't expect the patch to work correctly, because it replaces > _stronger_ memory barriers with _weaker_ SMP barriers. However, looking at > the blackfin's definitions of SMP barriers I see that it uses extra stuff that > should _also_ be used in the definitions of the mandatory barriers. > > In my opinion is an architecture problem, not the freezer code problem.
OK, we have a patch pending locally which populates all barriers with this logic, but based on my understanding of things, that didnt seem correct. i guess i'm reading too much into the names ... i'd expect the opposite behavior where "rmb" is only for UP needs while "smp_rmb" is a rmb which additionally covers SMP. -mike -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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