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SubjectRe: [PATCH 5/5] perf, x86: Add support for AMD family 15h core counters
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On Thu, 2011-02-03 at 10:00 +0100, Robert Richter wrote:
>
>
> ok, nb events may be implemented independent from core events in a
> separate struct pmu.
>
> I still would prefer a lookup table for counter addresses. Adding a
> shift parameter to struct x86_pmu to do a
>
> addr = base + (index << shift)
>
> seems to me a quite special solution that may not be reused in other
> implementations

What other implementations? I hope people will not re-arrange the MSR
layout on every new model, that'd be quite annoying.

> while a lookup table is more generic. I also don't
> see a performance or memory impact there.

Well it is an extra pointer chase and data cache hit just to get
something you can trivially compute.

> Anyway, a shift parameter would work too. What do you think?

I think the alternatives thing is probably nicest, except for having to
write the bits in asm.



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