Messages in this thread | | | Date | Thu, 3 Feb 2011 10:00:01 +0100 | From | Robert Richter <> | Subject | Re: [PATCH 5/5] perf, x86: Add support for AMD family 15h core counters |
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On 02.02.11 17:44:22, Stephane Eranian wrote: > On Wed, Feb 2, 2011 at 6:29 PM, Peter Zijlstra <peterz@infradead.org> wrote: > > On Wed, 2011-02-02 at 18:24 +0100, Robert Richter wrote: > >> On 02.02.11 12:03:18, Peter Zijlstra wrote: > >> > Why this and not something like x86_pmu.perfctr + (index << 1)? > >> > You could even use alternatives. > >> > >> I was thinking about this. The main reason is the implementation of > >> northbridge counters, the range is in MSRC001_02[47:40]. This would > >> add more complexity then. Using a table would be something like > >> > >> unsigned int eventsel_f15h[] = { > >> MSR_F15H_PERF_CTL, > >> MSR_F15H_PERF_CTL + 2, > >> MSR_F15H_PERF_CTL + 4, > >> MSR_F15H_PERF_CTL + 6, > >> MSR_F15H_PERF_CTL + 8, > >> MSR_F15H_PERF_CTL + 10, > >> MSR_F15H_NB_PERF_CTL, > >> MSR_F15H_NB_PERF_CTL + 2, > >> MSR_F15H_NB_PERF_CTL + 6, > >> MSR_F15H_NB_PERF_CTL + 8, > >> }; > >> > >> We don't need to change the address generation for this. Otherwise we > >> need to introduce more logic for the calculation. > >> > >> Also, were could be potential easier implementations for fixed > >> counters, BTS, P4, IBS, etc. But didn't look that close at it. > >> > >> (Btw, I am not yet sure if NB counters shouldn't better start at index > >> 16 or so to reserve space for perf counter expansion.) > > > > Now that the NB PMU is completely separate from the core PMU, wouldn't > > it make more sense to implement that as a separate entity just like the > > intel uncore bits? > > I agree on this.
Peter,
ok, nb events may be implemented independent from core events in a separate struct pmu.
I still would prefer a lookup table for counter addresses. Adding a shift parameter to struct x86_pmu to do a
addr = base + (index << shift)
seems to me a quite special solution that may not be reused in other implementations, while a lookup table is more generic. I also don't see a performance or memory impact there.
Anyway, a shift parameter would work too. What do you think?
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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