Messages in this thread | | | From | Linus Torvalds <> | Date | Thu, 3 Feb 2011 11:48:41 -0800 | Subject | Re: [patch] x86, mm: avoid stale tlb entries by clearing prev mm_cpumask after switching mm |
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On Thu, Feb 3, 2011 at 11:34 AM, Suresh Siddha <suresh.b.siddha@intel.com> wrote: > > True. 'stale' is the wrong word. Do you want me to send a corrected one > by replacing it with 'bogus'?
Please.
> my understanding is that unless we end up using that TLB entry, we will > not have the issues like machine checks due to cacheability issues etc. > If it is not global, upcoming cr3 change will flush it and meanwhile I > don't think there is a scenario where we refer to these user-addresses.
Quite possible. The situation I envisioned was the same speculative memory access that causes the TLB fill to also cause a cache fill - for a noncacheable region (because the bogus TLB entry sets the random address to cacheable).
And then what happens when somebody else accesses the same memory noncacheably (through a valid TLB entry), and finds it in the cache?
I dunno. Not really important. The important part is the "possible random bogus TLB entry", the fact that the CPU can act strangely after that is pretty much a given.
Linus
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