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SubjectRe: [PATCH v2 -tip] perf: x86, add SandyBridge support

* Lin Ming <ming.m.lin@intel.com> wrote:

> > In other words, bit 0-3 of the umask cannot be zero.
>
> I got the umask from "Table 30-20. PEBS Performance Events for Intel
> microarchitecture code name Sandy Bridge".
>
> But from "Table A-2. Non-Architectural Performance Events In the Processor Core
> for Intel Core Processor 2xxx Series", the combinations are needed as you show
> above.
>
> Which one is correct?

Since you have access to the hardware, could you please test and see it in practice
which one is correct?

Thanks,

Ingo


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