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    Subject[PATCH 3/5] perf, x86: Add new AMD family 15h msrs to perfctr reservation code
    Date
    This patch allows the reservation of perfctrs with new msr addresses
    introduced for AMD cpu family 15h (0xc0010200/0xc0010201, etc).

    Signed-off-by: Robert Richter <robert.richter@amd.com>
    ---
    arch/x86/kernel/cpu/perfctr-watchdog.c | 4 ++++
    1 files changed, 4 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
    index d5a2366..966512b 100644
    --- a/arch/x86/kernel/cpu/perfctr-watchdog.c
    +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
    @@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
    /* returns the bit offset of the performance counter register */
    switch (boot_cpu_data.x86_vendor) {
    case X86_VENDOR_AMD:
    + if (msr >= MSR_F15H_PERF_CTR)
    + return (msr - MSR_F15H_PERF_CTR) >> 1;
    return msr - MSR_K7_PERFCTR0;
    case X86_VENDOR_INTEL:
    if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
    @@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
    /* returns the bit offset of the event selection register */
    switch (boot_cpu_data.x86_vendor) {
    case X86_VENDOR_AMD:
    + if (msr >= MSR_F15H_PERF_CTL)
    + return (msr - MSR_F15H_PERF_CTL) >> 1;
    return msr - MSR_K7_EVNTSEL0;
    case X86_VENDOR_INTEL:
    if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
    --
    1.7.3.4



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