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    SubjectRe: [PATCH 0/2] jump label: 2.6.38 updates
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    On Wed, Feb 16, 2011 at 10:51 PM, Will Simoneau <simoneau@ele.uri.edu> wrote:
    > On 12:41 Wed 16 Feb     , Will Newton wrote:
    >> On Wed, Feb 16, 2011 at 12:18 PM, Steven Rostedt <rostedt@goodmis.org> wrote:
    >> > I'm curious, how is cmpxchg() implemented on this architecture? As there
    >> > are several places in the kernel that uses this on regular variables
    >> > without any "accessor" functions.
    >>
    >> We can invalidate the cache manually. The current cpu will see the new
    >> value (post-cache invalidate) and the other cpus will see either the
    >> old value or the new value depending on whether they read before or
    >> after the invalidate, which is racy but I don't think it is
    >> problematic. Unless I'm missing something...
    >
    > If I understand this correctly, the manual invalidates must propagate to
    > all CPUs that potentially read the value, even if there is no
    > contention. Doesn't this involve IPIs? How does it not suck?

    The cache is shared between cores (in that regard it's more like a
    hyper-threaded core than a true multi-core) so is completely coherent,
    so this is the one bit that doesn't really suck! Having spoken to our
    hardware guys I'm confident that we'll only ever build a handful of
    chip designs with the current way of doing ll/sc and hopefully future
    cores will do this the "right" way.
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