Messages in this thread | | | Date | Thu, 17 Feb 2011 11:03:10 -0500 | From | Mathieu Desnoyers <> | Subject | Re: [PATCH 0/2] jump label: 2.6.38 updates |
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* H. Peter Anvin (hpa@zytor.com) wrote: > On 02/16/2011 05:55 PM, Masami Hiramatsu wrote: > > > > Hmm, I think that is miss-coding ll/sc. > > If I understand correctly, usually cache invalidation should be done > > right before storing value, as MSI protocol does. > > (or, sc should atomically invalidate the cache line) > > > > I suspect in this case one should flush the cache line before ll (a > cache flush will typically invalidate the ll/sc link.)
hrm, but if you have:
invalidate -> interrupt read (fetch the invalidated cacheline) ll sc
you basically end up in a situation similar to not having any invalidate, no ? AFAIU, disabling interrupts around the whole ll-sc-invalidate (or invalidate-ll-sc) seems required for this specific architecture, so the invalidation is made "atomic" with the ll-sc pair from the point of view of one hardware thread.
Mathieu
> > -hpa > > -- > H. Peter Anvin, Intel Open Source Technology Center > I work for Intel. I don't speak on their behalf. >
-- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com
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