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Subject[173/272] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
2.6.37-stable review patch.  If anyone has any objections, please let us know.


From: Changhwan Youn <>

commit a50eb1c7680973f5441ca20ac4da0af2055d0d87 upstream.

This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer

Signed-off-by: Changhwan Youn <>
Cc: Catalin Marinas <>
Cc: Russell King <>
Signed-off-by: Kukjin Kim <>
Signed-off-by: Greg Kroah-Hartman <>

arch/arm/mach-s5pv310/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_ini

- l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+ l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);

return 0;

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