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    SubjectRe: [PATCH] Add support for multiple MSI on x86

    * Micha Nelissen <micha@neli.hopto.org> wrote:

    > Ingo Molnar wrote:
    > >* Micha Nelissen <micha@neli.hopto.org> wrote:
    > >>Patch is based on earlier patch from Matthew Wilcox.
    > >
    > >Hm, there's an awful lot of 'background', 'implementation',
    > >'advantages', 'disadvantages', 'testing' description missing.
    >
    > Sorry, my bad, wrong assumption that this would be common knowledge.

    When it comes to changes done to a kernel tree used by millions of people then
    common knowledge and mundane details need to be written down, in painstaking detail.

    You cannot really err when it comes to details: i've reviewed over a ten thousand
    patches in my life and i've yet to see a single one where the description was too
    verbose ;-)

    > PCI devices interrupt the CPU using 'legacy' INTx; or PCI-e devices
    > can do a special write, called an MSI (message signaled interrupt).
    > The interrupt vector is chosen by the CPU, different devices use
    > different vectors so that software can keep the interrupt sources
    > separate (instead of using shared INTx "lines").
    >
    > Most PCI-e devices support what's called MSI-X, but not all do.
    > Especially for FPGA based endpoints it's easier to implement only
    > 'regular' MSI support. MSI-X basically involves implementing a
    > lookup table that maps interrupt types in the device to interrupt
    > vectors for the CPU. 'Regular' MSI (non MSI-X) only supports a
    > contiguous block of interrupt vectors: a base vector with a vector
    > count (which is a power of 2).
    >
    > The x86 code to allocate these interrupt vectors does not handle the
    > <> 1 vector count case; it would return that it could only handle 1.
    > So either device drivers had 1 MSI, or the device should support
    > MSI-X to have multiple interrupts (and handlers) for one device.
    >
    > This patch adds the needed code to support multiple MSI per device.
    >
    > Advantages: separate interrupt handlers for separate tasks in the
    > device. This allows device drivers to be better structured. Easy
    > 'diagnostics' due to /proc/interrupts counting number of interrupts
    > for separate functionality separately.
    >
    > Disadvantages: more complex code due to requirement that it is a
    > contiguous block, so needs some effort to look for a free block with
    > the requested count.
    >
    > Tested: on an Atom platform, with a Xilinx based PCI-e core in FPGA.
    >
    > Please review; thanks,

    That was a good description, thanks Micha!

    Ingo


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