Messages in this thread | | | Date | Tue, 1 Feb 2011 19:51:15 +0100 | From | Borislav Petkov <> | Subject | Re: [EDAC-AMD64] Display correct RAM sizes in ganged mode on F10 CPUs |
| |
On Sat, Jan 29, 2011 at 04:15:31PM -0500, Markus Trippelsdorf wrote: > The EDAC_AMD64 module displays only half the actual memory size, when > RAM is running in ganged mode on F10 CPUs. Fix this by moving the the > conversion factor check out of the if block, where it is never reached. > > With this patch: > > Unganged: > amd64: DRAM ECC enabled. > EDAC amd64: F10h detected (node 0). > EDAC amd64: using x4 syndromes. > EDAC MC: DCT0 chip selects: > kernel: EDAC amd64: MC: 0: 1024MB 1: 1024MB > kernel: EDAC amd64: MC: 2: 1024MB 3: 1024MB > kernel: EDAC amd64: MC: 4: 0MB 5: 0MB > kernel: EDAC amd64: MC: 6: 0MB 7: 0MB > kernel: EDAC MC: DCT1 chip selects: > kernel: EDAC amd64: MC: 0: 1024MB 1: 1024MB > kernel: EDAC amd64: MC: 2: 1024MB 3: 1024MB > kernel: EDAC amd64: MC: 4: 0MB 5: 0MB > kernel: EDAC amd64: MC: 6: 0MB 7: 0MB > kernel: EDAC amd64: MCT channel count: 2
Hmm, can you send me your whole dmesg without your patch, dmidecode output and the exact model of your DIMMs.
Thanks.
-- Regards/Gruss, Boris.
Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach General Managers: Alberto Bozzo, Andrew Bowd Registration: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632
| |