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    Subject[08/80] drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
    3.0-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Eric Anholt <eric@anholt.net>

    commit 406478dc911e16677fbd9c84d1d50cdffbc031ab upstream.

    Fixes rendering failures in Unigine Tropics and Sanctuary and the mesa
    "fire" demo.

    Signed-off-by: Eric Anholt <eric@anholt.net>
    Signed-off-by: Keith Packard <keithp@keithp.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    drivers/gpu/drm/i915/i915_reg.h | 3 +++
    drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
    2 files changed, 12 insertions(+)

    --- a/drivers/gpu/drm/i915/i915_reg.h
    +++ b/drivers/gpu/drm/i915/i915_reg.h
    @@ -3370,6 +3370,9 @@

    #define GT_FIFO_FREE_ENTRIES 0x120008

    +#define GEN6_UCGCTL2 0x9404
    +# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
    +
    #define GEN6_RPNSWREQ 0xA008
    #define GEN6_TURBO_DISABLE (1<<31)
    #define GEN6_FREQUENCY(x) ((x)<<25)
    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -7405,6 +7405,15 @@ static void gen6_init_clock_gating(struc
    I915_WRITE(WM2_LP_ILK, 0);
    I915_WRITE(WM1_LP_ILK, 0);

    + /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
    + * gating disable must be set. Failure to set it results in
    + * flickering pixels due to Z write ordering failures after
    + * some amount of runtime in the Mesa "fire" demo, and Unigine
    + * Sanctuary and Tropics, and apparently anything else with
    + * alpha test or pixel discard.
    + */
    + I915_WRITE(GEN6_UCGCTL2, GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
    +
    /*
    * According to the spec the following bits should be
    * set in order to enable memory self-refresh and fbc:



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