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SubjectRe: [PATCH 05/12] perf_events: add LBR mappings for PERF_SAMPLE_BRANCH filters (v2)
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On Fri, 2011-10-14 at 14:37 +0200, Stephane Eranian wrote:
> void intel_pmu_lbr_init_atom(void)
> {
> + /*
> + * only models starting at stepping 10 seems
> + * to have an operational LBR which can freeze
> + * on PMU interrupt
> + */
> + if (boot_cpu_data.x86_mask < 10) {
> + pr_cont("LBR disabled due to erratum");
> + return;
> + }

Shouldn't that be a separate patch?


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