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SubjectRe: [PATCH] perf_events: fix and improve x86 event scheduling
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On Thu, 2011-11-10 at 16:09 +0100, Stephane Eranian wrote:
> What are the configs for which you have failures on Intel?
>
Continuing to use Core2 as an example platform:

cycles,cycles,instructions,instructions

They all have weight 3, yet the masks are not the same, it'll assign
them like: pmc0, pmc1, fp-instructions, fail

Counter rotation will make sure the next attempt looks like:

instructions,cycles,cycles,instructions

Which will work correctly since it'll do: pmc0, pmc1, fp-cycles,
fp-instructions.

Its usually not a really big deal, but I ran into it few months ago and
noticed it because the scaled values weren't what I was expecting them
to be, took me a while to figure out wth happened.




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