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SubjectRe: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order setup by IO control
Hi Grant,

It seems this patch Toshiharu posted in 20-July remains not to be
reviewed by you.

Could you review this patch and merge to your tree ?

Thanks in advance,

--
tomoya
ROHM Co., Ltd.

(2011/07/20 14:56), Toshiharu Okada wrote:
> This patch supports a spi mode setup and bit order setup by IO control.
> spi mode: mode 0 to mode 3
> bit order: LSB first, MSB first
>
> Signed-off-by: Toshiharu Okada<toshiharu-linux@dsn.okisemi.com>
> ---
> drivers/spi/spi_topcliff_pch.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
> index 79e48d4..dec83c9 100644
> --- a/drivers/spi/spi_topcliff_pch.c
> +++ b/drivers/spi/spi_topcliff_pch.c
> @@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> master->num_chipselect = PCH_MAX_CS;
> master->setup = pch_spi_setup;
> master->transfer = pch_spi_transfer;
> + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
> dev_dbg(&pdev->dev,
> "%s transfer member of SPI master initialized\n", __func__);
>




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