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SubjectRe: [PATCH 1/8] x86, apic.c: Disable irq0 if CPU enables ARAT for local apic timer
Date
"Yu, Fenghua" <fenghua.yu@intel.com> writes:
>
> SC1200 WDT DRIVER
> M: Zwane Mwaikambo <zwane@arm.linux.org.uk>
> S: Maintained
> F: drivers/watchdog/sc1200wdt.c
>
> I was hoping Zwane knows which PCI quirks depends on CPU0.

At least one AMD SIS chipset relied on IRQ0 always being on CPU0
Not sure we got a quirk for it because the existing code handled it
(I guess it's reasonable to just blacklist for all of SIS,
i don't think they ever did anything multi-socket)
Alan may remember more.

-Andi

--
ak@linux.intel.com -- Speaking for myself only


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