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    SubjectRE: [PATCHv4] DMAEngine: Define interleaved transfer request api
    On Sat, Oct 15, 2011 at 7:26 AM, Jassi Brar <>
    > On 15 October 2011 00:45, Bounine, Alexandre
    > <> wrote:
    > >> But doesn't the info, pointed to by this (void *), remain same for
    > >> every
    > >> transfer to a particular target/remote device ?
    > > No. An address within the target may (and most likely will) be
    changed for
    > > every transfer. Target destination ID will be the same for given
    virtual channel.
    > >
    > Thanks for the info.
    > > Virtual channel may bring the same challenge and I may need a
    channel locking
    > > if more than one requester try to read/write data to the same target
    RIO device.
    > >
    > One can't avoid taking care of locking, but using virtual channels
    > keeps the dma_chan usage consistent.
    Using virtual channels adds layers of complexity which may be avoided
    simple API changes:
    - virtual channel allocation: statically vs. dynamically
    - linking virtual channel to the physical one

    > RapidIO supports 34(32+2), 50(48+2) and 66(64+2) bit addressing
    > which makes me wonder if the (upper or lower) 2 bits could be attached
    > to
    > the identity of the target device ?
    > (tsi721 driver actually discards the upper 2 bits while claiming to
    > support
    > 66bit addressing so I couldn't make anything out of it and specs don't
    > seem to say much about it)
    > If there is no user of 66bit addressing and isn't coming in very near
    > future,
    > we might as well drop that case for now(tsi721 already does) because
    > that 'completeness' of support modifies the semantics of dmaengine
    > today for no real use.
    This is marked to be fixed in tsi721 driver. Also, this is a local
    and changing it that does not affect other components of the RIO
    Contrary to that, defining an upper layer affects all future development
    may result in greater pain if it needs to be adjusted later.


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