Messages in this thread | | | Date | Fri, 14 Oct 2011 19:21:45 +0530 | Subject | Re: [PATCHv5] DMAEngine: Define interleaved transfer request api | From | Jassi Brar <> |
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On 14 October 2011 19:01, Vinod Koul <vinod.koul@intel.com> wrote: > On Fri, 2011-10-14 at 17:21 +0530, Jassi Brar wrote: >> On 14 October 2011 13:02, Barry Song <21cnbao@gmail.com> wrote: >> > >> > what if i want a cyclic interleaved transfer? i think the cyclic >> > interleaved transfer is what i want for audio dma. >> > >> ... we need to restore 'bool frm_irq' and add new 'bool cyclic' that >> would replay the transfer(i.e, reset dma-pointers to src_start & dst_start) >> after 'numf' frames have been transferred. > I was thinking more on lines to have this conveyed thru a flag. > Sorry don't see exactly what you mean. frm_irq and numf are independent of each other and could cover more cases than a single flag.
> Anyway I plan to work on merging device_prep_slave_sg and > device_prep_cyclic to single API. Think more of device_prep_cyclic as > special case with sg length one and flag to tell dmac its cyclic. > AFAIK, usually the ring buffer is divided into N (>1) different periods that need to be transferred in endless loop.
> Similarly here we could use/define this flag to say this transfer is > also cyclic in nature and dmac then reloads the list again. > That way any prep can be made cyclic in nature by just using this flag. > Some cyclic transfers might want callback done after each period/frame while some not. We can't cover using just one flag.
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