Messages in this thread Patch in this message | | | From | Catalin Marinas <> | Subject | [PATCH v4 14/19] ARM: LPAE: Add SMP support for the 3-level page table format | Date | Mon, 24 Jan 2011 17:55:56 +0000 |
| |
With 3-level page tables, starting secondary CPUs required allocating the pgd as well. Since LPAE Linux uses TTBR1 for the kernel page tables, this patch reorders the CPU setup call in the head.S file so that the swapper_pg_dir is used. TTBR0 is set to the value generated by the primary CPU.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> ---
There was a comment that secondary_startup hunk below should not reorder the code but pass two registers for TTBR0 and TTBR1. I still find this approach simpler __v7_setup never programs TTBR0 so it would ignore one of the registers.
arch/arm/kernel/head.S | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index d96986c..bade113 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -331,6 +331,10 @@ ENTRY(secondary_startup) THUMB( it eq ) @ force fixup-able long branch encoding beq __error_p + pgtbl r4 + add r12, r10, #BSYM(PROCINFO_INITFUNC) + blx r12 @ initialise processor + @ (return control reg) /* * Use the page tables supplied from __cpu_up. */ @@ -338,12 +342,8 @@ ENTRY(secondary_startup) ldmia r4, {r5, r7, r12} @ address to jump to after sub r4, r4, r5 @ mmu has been enabled ldr r4, [r7, r4] @ get secondary_data.pgdir - adr lr, BSYM(__enable_mmu) @ return address mov r13, r12 @ __secondary_switched address - ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor - @ (return control reg) - THUMB( add r12, r10, #PROCINFO_INITFUNC ) - THUMB( mov pc, r12 ) + b __enable_mmu ENDPROC(secondary_startup) /*
| |