Messages in this thread | | | Date | Wed, 12 Jan 2011 09:19:53 -0800 | From | "H. Peter Anvin" <> | Subject | Re: [sodaville] [PATCH 10/15] x86/ioapic: Add OF bindings for IO-APIC |
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On 01/12/2011 09:07 AM, Sebastian Andrzej Siewior wrote: >> >> I'm confused here. Are there multiple ioapic's described by a single >> device tree node? > > Yes, the CE4100 has two IO-APICs. It looks like the first one is > responsible for the "legacy devices" (like RTC) and the second one is > used for the "extra devices" like SPI controller, USB, ... The UART > however is not on the first IO-APIC but on the second. > > Those two IO-APICs are not cascaded. The device tree contains the line > number of device to the io apic. The kernel computes then interrupt > number based on gsi_base + line_number where gsi_base is incremented by > the number of entries[0]. This interrupt number (gsi_base + line) is then > sent via apic bus to lapic which reports it as the active interrupt > source. >
That's normal multiple IOAPIC behavior (and multiple IOAPICs is a common thing), but why use the same device tree node for both?
-hpa
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