Messages in this thread | | | Date | Wed, 15 Sep 2010 19:28:05 +0200 | From | Robert Richter <> | Subject | Re: [PATCH] perf, x86: catch spurious interrupts after disabling counters |
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On 15.09.10 13:02:22, Cyrill Gorcunov wrote: > > what's for sure, is that you can have an interrupt in flight by the time > > you disable. > > > > I fear you can x86_pmu_stop() > > if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { > > ---> active_mask will be cleared here for sure > ---> but counter still ticks, say nmi happens active_mask > ---> is cleared, but NMI can still happen and gets buffered > ---> before you disable counter in real > > x86_pmu.disable(event); > cpuc->events[hwc->idx] = NULL; > WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); > hwc->state |= PERF_HES_STOPPED; > } > > No?
I tried reordering this too, but it didn't fix it.
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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