Messages in this thread | | | Date | Wed, 4 Aug 2010 20:48:06 +0200 | From | Robert Richter <> | Subject | Re: A question of perf NMI handler |
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(cc'ing Andi)
On 04.08.10 12:39:30, Cyrill Gorcunov wrote: > On Wed, Aug 04, 2010 at 12:20:26PM -0400, Don Zickus wrote:
> > there. The problem is the bits in register 0x61 are not always set > > correctly in the case of SERRs (well at least in all the cases I have > > dealt with). So you can easily can a flood of unknown nmis from an SERR > > and register 0x61 would have the PERR/SERR bits set to 0. Fun, huh? > > if there is nothing in nmi_sc the code flows into another branch. And > it hits the problem of perf events eating all nmi giving no chance the > others. So we take if (!(reason & 0xc0)) case and hit DIE_NMI_IPI > (/me scratching the head why it's not under CONFIG_X86_LOCAL_APIC) and > drop all code, unpleasant.
Only the upper 2 bits in io_61h indicate the nmi reason, so in case of (!(reason & 0xc0)) the source simply can not be determined and all nmi handlers in the chain must be called (DIE_NMI/DIE_NMI_IPI). The perfctr handler then stops it.
So you can decide to either get an unrecovered nmi panic triggered by a perfctr or losing unknown nmis from other sources. Maybe this can be fixed by implementing handlers for those sources.
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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