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    SubjectRe: A question of perf NMI handler
    On Wed, Aug 04, 2010 at 05:02:41PM +0200, Peter Zijlstra wrote:
    > On Wed, 2010-08-04 at 10:52 -0400, Don Zickus wrote:
    > > > Right so I looked up your thing and while that limits the damage in that
    > > > at some point it will let NMIs pass, it will still consume too many.
    > > > Meaning that Yinghai will have to potentially press his NMI button
    > > > several times before it registers.
    > >
    > > Ok. Thanks for reviewing. How does it consume to many? I probably don't
    > > understand how perf is being used in the non-simple scenarios.
    > Suppose you have 4 counters (AMD, intel-nhm+), when more than 2 overflow
    > the first will raise the PMI, if the other 2+ overflow before we disable
    > the PMU it will try to raise 2+ more PMIs, but because hardware only has
    > a single interrupt pending bit it will at most cause a single extra
    > interrupt after we finish servicing the first one.
    > So then the first interrupt will see 3+ overflows, return 3+, and will
    > thus eat 2+ NMIs, only one of which will be the pending interrupt,
    > leaving 1+ NMIs from other sources to consume unhandled.
    > In which case Yinghai will have to press his NMI button 2+ times before
    > it registers.
    > That said, that might be a better situation than always consuming
    > unknown NMIs..

    Well, first I guess having Yinghai CC'ed is a bonus ;)
    The second thing is that I don't get why perf handler can't be _last_
    call in default_do_nmi, if there were any nmi with reason (serr or parity)
    I think they should be calling first which of course don't eliminate
    the former issue but somewhat make it weaken.

    -- Cyrill

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