Messages in this thread | | | Date | Mon, 16 Aug 2010 19:16:10 +0200 | From | Robert Richter <> | Subject | Re: [PATCH -v2] perf, x86: try to handle unknown nmis with running perfctrs |
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On 16.08.10 12:27:06, Cyrill Gorcunov wrote: > On Mon, Aug 16, 2010 at 04:48:36PM +0200, Peter Zijlstra wrote: > > I liked the one without funny timestamps in better, the whole timestamps > > thing just feels too fragile. > > > > Me too, the former Roberts patch (if I'm not missing something) looks good > to me. > > > > > Relying on handled > 1 to arm the back-to-back filter seems doable.
Peter, I will rip out the timestamp code from the -v2 patch. My first patch does not deal with a 2-1-0 sequence, so it has false positives. We do not necessarily need the timestamps if back-to-back nmis are rare. Without using timestamps the statistically lost ratio for unknown nmis will be as the ratio for back-to-back nmis, with timestamps we could catch almost every unknown nmi. So if we encounter problems we could still implement timestamp code on top.
> It's doable _but_ I think there is nothing we can do, there is no > way (at least I known of) to check if there is latched nmi from > perf counters. We only can assume that if there multiple counters > overflowed most probably the next unknown nmi has the same nature, > ie it came from perf.
As said, I think with timestamps we could be able to detect 100% of the unknown nmis. I guess we get now more than 90% with mutliple counters, and 100% with a single counter running. So, this is already more than a simple improvement.
> Yes, we can loose real unknown nmi in this > case but I think this is justified trade off. If an user need > a precise counting of unknown nmis he should not arm perf events > at all, if there an user with nmi button (guys where did you get this > magic buttuns? i need one ;) he better to not arm perf events too > otherwise he might have to click twice > > (and of course we should keep in mind Andi's proposal but it > is a next step I think).
Yes, this patch is the first step, now we can change the nmi handler priority. The perf handler must not have the lowest priority anymore.
> > (Also, you didn't deal with the TSC going backwards..)
Does this also happen in the case of a back-to-back nmi? I don't know the conditions for a backward running TSC. Maybe, if an nmi is retriggered the TSC wont be adjusted by a negative offset, I don't know...
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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