lkml.org 
[lkml]   [2010]   [Jul]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH + an old question] firewire: ohci: use memory barriers to order descriptor updates
On 27 Jul, Stefan Richter wrote:
> 2. a write memory barrier between branch_address update and wake-up of
> the DMA unit by MMIO register write.
>
> This patch adds only barrier 1.
>
> Barrier 2 is implicit in writel() on most machines --- or at least I
> think it is. See this from arch/alpha/include/asm/io.h:

Typo, arch/x86/include/asm/io.h was meant.

> #define build_mmio_write(name, size, type, reg, barrier) \
> static inline void name(type val, volatile void __iomem *addr) \
> { asm volatile("mov" size " %0,%1": :reg (val), \
> "m" (*(volatile type __force *)addr) barrier); }
>
> build_mmio_write(writel, "l", unsigned int, "r", :"memory")
>
> Does this order the mmio write relative to previous memory writes?
--
Stefan Richter
-=====-==-=- -=== ==-==
http://arcgraph.de/sr/



\
 
 \ /
  Last update: 2010-07-27 13:25    [W:0.051 / U:1.024 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site