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    SubjectRe: [patch 1/2] x86_64 page fault NMI-safe
    On Wed, Jul 14, 2010 at 2:45 PM, Maciej W. Rozycki <> wrote:
    > On Wed, 14 Jul 2010, Linus Torvalds wrote:
    >> No. As mentioned, there is no such counter in real hardware either.
    >  There is a 1-bit counter or actually a latch.

    Well, that's what our single-word flag is too.

    >> Look at what happens for the not-nested case:
    >>  - NMI1 triggers. The CPU takes a fault, and runs the NMI handler with
    >> NMI's disabled
    >  Correct.
    >>  - NMI2 triggers. Nothing happens, the NMI's are disabled.
    >  The NMI latch records the second NMI.  Note this is edge-sensitive like
    > the NMI line itself.
    >>  - NMI3 triggers. Again, nothing happens, the NMI's are still disabled
    >  Correct.
    >>  - the NMI handler returns.
    >>  - What happens now?
    >  NMI2 latched above causes the NMI handler to be invoked as the next
    > instruction after IRET.  The latch is cleared as the interrupt is taken.
    >> How many NMI interrupts do you get? ONE. Exactly like my "emulate it
    >> in software" approach. The hardware doesn't have any counters for
    >> pending NMI's either. Why should the software emulation have them?
    >  Two. :)

    You just count differently. I don't count the first one (the "real"
    NMI). That obviously happens. So I only count how many interrupts we
    need to fake. That's my "one". That's the one that happens as a result
    of the fault that we take on the iret in the emulated model.

    So there is no need to count anything. We take a fault on the iret if
    we got a nested NMI (regardless of how _many_ such nested NMI's we
    took). That's the "latch", exactly like in the hardware. No counter.

    (Yeah, yeah, you can call it a "one-bit counter", but I don't think
    that's a counter. It's just a bit of information).

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