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    SubjectRe: [PATCH 09/18] Robust TSC compensation
    On 07/13/2010 11:42 AM, David S. Ahern wrote:
    >
    > On 07/13/10 15:15, Zachary Amsden wrote:
    >
    >
    >>> What prevents a vcpu from seeing its TSC go backwards, in case the first
    >>> write in the 5 second window is smaller than the victim vcpu's last
    >>> visible TSC value ?
    >>>
    >>>
    >> Nothing, unfortunately. However, the TSC would already have to be out
    >> of sync in order for the problem to occur. It can never happen in
    >> normal circumstances on a stable hardware TSC except in one case;
    >> migration. During the CPU state transfer phase of migration, however,
    >>
    > What about across processor sockets? Aren't CPUs brought up at different
    > points such that their TSCs start at different times?
    >

    It depends on the platform. But it doesn't matter. The definition we
    use is different start TSCs == out of sync. Some systems have
    synchronized TSCs, some do not.

    See patch 18/18 - "Timekeeping documentation" for details.


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