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SubjectRe: [PATCH] x86/sfi: fix ioapic gsi range

> > Background:
> > In Moorestown/Medfield platforms, there is no legacy IRQs, all gsis
> > and irqs are one to one mapped, including those < 16. Specifically,
> > IRQ0 and IRQ1 are used for per-cpu timers. So without this patch,
> > IOAPIC pin to IRQ mapping is off by one.
>
> The patch looks mostly reasonable the comment is wrong.
>
> You may not use a 1-1 mapping if you don't have legacy irqs. Linux
> irqs 0-15 are the ISA irqs you may not use those irq numbers for
> something different on any architecture, but especially not on x86.
> The gsi numbers are firmware specific and you may treat however you
> want.

[jacob pan] If we don't have ISA irqs, why can't we have gsi# = irq#
for the legacy IRQ range? On Moorestown, we are re-using legacy irqs.
e.g.
sh-4.0# cat /proc/interrupts
CPU0 CPU1
0: 1512 0 IO-APIC-edge apbt0
1: 0 1482 IO-APIC-edge apbt1
9: 0 0 IO-APIC-fasteoi dw_spi
10: 0 0 IO-APIC-fasteoi mrst_i2c
11: 0 0 IO-APIC-fasteoi mrst_i2c
12: 0 0 IO-APIC-fasteoi mrst_i2c
23: 0 0 IO-APIC-fasteoi intel_scu_ipc
27: 21 0 IO-APIC-fasteoi



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