Messages in this thread | | | Date | Mon, 07 Jun 2010 17:30:59 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [PATCH] x86/sfi: fix ioapic gsi range |
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On 06/07/2010 05:24 PM, Eric W. Biederman wrote: > Jacob Pan <jacob.jun.pan@linux.intel.com> writes: > >> SFI based platforms should have zero based gsi_base for IOAPICs found in SFI >> tables. The current code sets gsi_base starting from 1 when registering ioapic. >> The result is that Moorestown platform would have wrong mp_gsi_routing for each >> ioapic. > > Yes starting at 1 is a bug. > >> Background: >> In Moorestown/Medfield platforms, there is no legacy IRQs, all gsis and irqs >> are one to one mapped, including those < 16. Specifically, IRQ0 and IRQ1 are >> used for per-cpu timers. So without this patch, IOAPIC pin to IRQ mapping is >> off by one. > > The patch looks mostly reasonable the comment is wrong. > > You may not use a 1-1 mapping if you don't have legacy irqs. Linux > irqs 0-15 are the ISA irqs you may not use those irq numbers for > something different on any architecture, but especially not on x86. > The gsi numbers are firmware specific and you may treat however you want. > > Does the following patch work for you? > > It appears I goofed when it was pointed out that gsi_end was inclusive and > didn't change the initialize. > > diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c > index 33f3563..5de84e5 100644 > --- a/arch/x86/kernel/apic/io_apic.c > +++ b/arch/x86/kernel/apic/io_apic.c > @@ -90,7 +90,7 @@ int nr_ioapics; > struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; > > /* The last gsi number used */ > -u32 gsi_end; > +u32 gsi_end = -1; >
This seems like asking for signedness problems, especially since this is used in range compares all the time. The real problem here is that gsi_end is inclusive, which is almost always the wrong thing for the endpoint of a range. Instead we should have the last number used plus one; perhaps it should be called gsi_next or gsi_free.
-hpa
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