Messages in this thread | | | Date | Mon, 28 Jun 2010 09:08:40 -0700 | From | Richard Henderson <> | Subject | Re: Problems with alpha/pci + radeon/ttm |
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On 06/28/2010 02:03 AM, Michael Cree wrote: > On 28/06/10 11:14, Dave Airlie wrote: >> The bus error is caused by the kernel, its something alpha specific >> with how mmap works, >> I'm not sure if alpha needs some special mmap flags or something, > > Neither am I. All I know is that Alpha reorders CPU instructions more > aggressively than most other architectures, the page map size is 8kB, > and memory accesses must be aligned to the datum size.
There are no special mmap flags on alpha. The non-cacheable property is a function of the physical address (e.g. bit 40 set for ev5), and this has already been taken care of by the kernel.
r~
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