Messages in this thread Patch in this message | | | From | Borislav Petkov <> | Subject | [PATCH 6/6] amd64_edac: Fix DCT base address selector | Date | Tue, 1 Jun 2010 15:29:31 +0200 |
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From: Borislav Petkov <borislav.petkov@amd.com>
The correct check is to verify whether in high range we're below 4GB and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM Requests" in the F10h BKDG.
Cc: <stable@kernel.org> # .32.x .33.x Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> --- drivers/edac/amd64_edac.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 80600f1..6866b98 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1432,7 +1432,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, u64 chan_off; if (hi_range_sel) { - if (!(dct_sel_base_addr & 0xFFFFF800) && + if (!(dct_sel_base_addr & 0xFFFF0000) && hole_valid && (sys_addr >= 0x100000000ULL)) chan_off = hole_off << 16; else -- 1.7.1
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