Messages in this thread Patch in this message | | | Date | Mon, 31 May 2010 20:45:53 +0400 | From | Cyrill Gorcunov <> | Subject | Re: [RFC] perf, x86: Segregate PMU workaraunds into x86_pmu_quirk_ops structure |
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On Sat, May 29, 2010 at 08:33:10PM +0200, Peter Zijlstra wrote: > > On Sat, 2010-05-29 at 22:24 +0400, Cyrill Gorcunov wrote: > > @@ -924,7 +930,11 @@ x86_perf_event_set_period(struct perf_ev > > */ > > atomic64_set(&hwc->prev_count, (u64)-left); > > > > - wrmsrl(hwc->event_base + idx, > > + if (x86_pmu.quirks.perfctr_write) > > + x86_pmu.quirks.perfctr_write(hwc->event_base + idx, > > + (u64)(-left) & x86_pmu.cntval_mask); > > + else > > + wrmsrl(hwc->event_base + idx, > > (u64)(-left) & x86_pmu.cntval_mask); > > This bit is rather ugly,.. not quite sure how to clean it up though. > Anybody got a bright idea? >
Yes, I know, only a bit lighter solution could be like in patch below, alternative instructions bring mess (and considering we may have paravirt turned on -- even more mess), jump labels... I didn't find them in tree, in which file(s) they are? I mean, are they under review now or merged in some place?
So I guess plain test may be more-less fine here, hmm?
-- Cyrill --- perf, x86: Make a second write to performance counter when needed
On Netburst cpu we need a second write to performance counter to be sure it's updated properly.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> --- arch/x86/kernel/cpu/perf_event.c | 10 ++++++++++ arch/x86/kernel/cpu/perf_event_p4.c | 9 +++++++++ 2 files changed, 19 insertions(+)
Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event.c ===================================================================== --- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event.c +++ linux-2.6.git/arch/x86/kernel/cpu/perf_event.c @@ -220,6 +220,7 @@ struct x86_pmu { struct perf_event *event); struct event_constraint *event_constraints; void (*quirks)(void); + int perfctr_second_write; int (*cpu_prepare)(int cpu); void (*cpu_starting)(int cpu); @@ -926,6 +927,15 @@ x86_perf_event_set_period(struct perf_ev atomic64_set(&hwc->prev_count, (u64)-left); wrmsrl(hwc->event_base + idx, + (u64)(-left) & x86_pmu.cntval_mask); + + /* + * Due to erratum on certan cpu we need + * a second write to be sure the register + * is updated properly + */ + if (x86_pmu.perfctr_second_write) + wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); perf_event_update_userpage(event); Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c ===================================================================== --- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event_p4.c +++ linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c @@ -829,6 +829,15 @@ static __initconst const struct x86_pmu .max_period = (1ULL << 39) - 1, .hw_config = p4_hw_config, .schedule_events = p4_pmu_schedule_events, + /* + * This handles erratum N15 in intel doc 249199-029, + * the counter may not be updated correctly on write + * so we need a second write operation to do the trick + * (the official workaround didn't work) + * + * the former idea is taken from OProfile code + */ + .perfctr_second_write = 1, }; static __init int p4_pmu_init(void)
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