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SubjectRe: [PATCH 3/3] alpha: Implement HW performance events on the EV67 and later CPUs.
On 4/05/2010, at 7:40 PM, Peter Zijlstra wrote:
> On Sat, 2010-05-01 at 11:55 +1200, Michael Cree wrote:
>> +/* I wonder what this is for ??? */
>> +void set_perf_event_pending(void)
>> +{
>> +}
> If the PMU Interrupt comes in as an NMI we cannot take locks and such
> from its handler. So what we do is queue that work to be ran later.
> The
> kernel has a fallback to run this stuff from the timer hardirq, but if
> the PMI is IRQ context (like ARM) you can simply call
> perf_event_do_pending() at its tail.

My understanding from the Alpha HW Ref. Man. and a brief look at the
kernel code is that the PMI comes in through the normal IRQ entry
point on the Alpha. It is a high priority interrupt and only a
machine check (i.e. detected hardware failure) can interrupt the PMU
interrupt handler. I don't know whether that is an issue for taking
locks or not and need advice on that.

I originally based the Alpha implementation on the Sparc
implementation and would've copied the set_perf_event_pending()
definition from the Sparc code, but I now see that newer Sparc code
does not have that definition nor does it call perf_event_do_pending()
in the interrupt handler.

So I need advice on whether to:

1) Just remove the set_perf_event_pending() definition so we are like
the Sparc code,

2) Add perf_event_do_pending() to the tail of the IRQ handler so we
are like the ARM code, or

3) Implement the following suggestion:

> Alternatively you can self-IPI like x86 does and run
> perf_event_do_pending() from there.

Another question is what are the observeable symptoms if an incorrect
option above is implemented?


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