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    Subject[patch 3/4] x86,perf: P4 PMU -- add missing bit in CCCR mask
    Should be there is a sake of RAW events.

    Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
    CC: Lin Ming <ming.m.lin@intel.com>
    CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
    CC: Ingo Molnar <mingo@elte.hu>
    CC: Frederic Weisbecker <fweisbec@gmail.com>
    ---
    arch/x86/include/asm/perf_event_p4.h | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    Index: linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
    =====================================================================
    --- linux-2.6.git.orig/arch/x86/include/asm/perf_event_p4.h
    +++ linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
    @@ -89,7 +89,8 @@
    P4_CCCR_ENABLE)

    /* HT mask */
    -#define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY)
    +#define P4_CCCR_MASK_HT \
    + (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY)

    #define P4_GEN_ESCR_EMASK(class, name, bit) \
    class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)


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