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SubjectRe: Rampant ext3/4 corruption on 2.6.34-rc7 with VIVT ARM (Marvell 88f5182)
On Fri, May 14, 2010 at 06:41:53PM +0100, Jamie Lokier wrote:
> Russell King - ARM Linux wrote:
> > On Thu, May 13, 2010 at 08:47:11AM +1000, Benjamin Herrenschmidt wrote:
> > > Now, in the case at hand, which is my ARM based NAS, I believe this
> > > is non cache-coherent and thus uses cache flush ops. I don't know ARM
> > > well enough but I would expect these to be implicit barriers. Russell ?
> > > Nico ?
> >
> > ARMv5 doesn't have a weak memory ordering model, and doesn't have any
> > memory barrier instructions.
>
> It does have buffered writes, doesn't it? Are they always flushed by
> the cache flush ops?

Surprisingly, for DMA it's something we've always done. Odd that.


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