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    SubjectRe: [RFC][PATCH 3/9] perf: export registerred pmus via sysfs
    On Wed, 2010-05-12 at 14:51 +0900, Paul Mundt wrote:
    > On Tue, May 11, 2010 at 11:48:42AM +0200, Peter Zijlstra wrote:

    > > No all the cpus would have the same event sources. I'm not sure if we
    > > can make sysfs understand that though (added GregKH and Kay to CC).
    > >
    > This is something I've been thinking about, too. On SH we have a
    > large set of perf counter events that are entirely dependent on the
    > configuration of the CPU they're on, with no requirement that these
    > configurations are identical on all CPUs in an SMP configuration.
    > As an example, it's possible to halve the L1 dcache and use that part of
    > it as a small and fast memory which has completely different events
    > associated with it from the regular L1 dcache events. These events would
    > be invalid on a CPU that was running with all cache ways enabled but
    > might also be valid on other CPUs that bolt these events to an extra SRAM
    > outside of the cache topology completely.
    > In any event, the events are at least consistent across all CPUs, it's
    > only which ones are valid on a given CPU at a given time that can change.

    So you're running with asymmetric SMP systems? I really hadn't
    considered that. Will this change at runtime or is it a system boot time

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